1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits, and more particularly to a test circuit built in a semiconductor integrated circuit having a plurality of data buses.
2. Description of the Prior Art
As the integration density of integrated circuit memories increases and hence the storage capacity thereof increases, an increased number of data buses is used and a memory cell array is divided into a plurality of blocks.
FIG. 1 is a block diagram of a conventional memory circuit which can simultaneously output four bits. Four pairs of data buses DB1-DB4 are shown in FIG. 1. Data read out from memory cells (not shown) through four pairs of data buses DB1-DB4 are output to the outside of the memory through sense amplifiers SA1-SA4 and buffers BUF1-BUF4, respectively.
A test circuit TC is provided in common to the four pairs of data buses DB1-DB4. In a test mode, the test circuit TC receives, via four pairs of MOS transistors MT1-MT4, data read out from the memory cells after writing test data therein, and outputs a pass/fail output signal to the outside of the memory through a pair of MOS transistors MT6 and the buffer BUF4. In the test mode, a test select signal TS, which is applied to the gates of the MOS transistors MT1-MT4 and MT6, is switched to a high level, so that these MOS transistors are turned ON. A pair of MOS transistors MT5 is interposed between the sense amplifier SA4 and the buffer BUF4. An inverted version of the test select signal TS is applied to the gates of the MOS transistors MT5.
FIG. 2 is a circuit diagram of a conventional 16-bit simultaneous test type memory. When all 16 data buses DB0-DB15 are maintained at a logically high level H, an output signal of a NAND gate G3 generates a high-level signal. In a test mode, a parallel-test enable signal PTE is maintained at H, and hence a NAND gate G4 and a NOR gate G5 are open. Thus, an output signal of the NAND gate G4 has a logically low level L, and the NOR gate G5 generates a low-level signal. As a result, a parallel-test output signal PTO output by a CMOS inverter consisting of transistors Ta and Tb is maintained at H. If at least one of the data buses DB0-DB15 is maintained at L (abnormal state) in the case where all the 16 bits of data are maintained at H in a normal state, the output signal of the NAND gate G1 switches to H, and an output signal of an OR gate G2 switches to H. Hence the output signal of the NAND gate G3 switches to L, and the output signal of the NAND gate G4 switches to H. Further, the output signal of the NOR gate G5 switches to H, and hence the output signal PTO of the CMOS inverter switches to L.
When all the 16 data buses DB0-DB15 are maintained at L, the output signals of the gates G1 and G3 are maintained at H and the output signal of the gate G2 is maintained at L. Hence, the output signal PTO of the CMOS inverter is maintained at H. If at least one of the data buses DB0-DB15 is maintained at H in the state where all the 16 bits of data are maintained at L in the normal state, the output signals of the gates G1 and G2 switch to L, and the output signal of the gate G3 switches to L. Hence, the output signal PTO of the CMOS inverter switches to L. In the manner as described above, 16 bits of data transferred through the data buses DB0-DB15 can be simultaneously tested. In the test mode in which the signal PTE is maintained at H, address buffers which pass address signals AB are disabled due to an inverted version of the signal PTE.
However, the conventional circuit shown in FIG. 1 has the following disadvantages. First, data read out from the memory cells are transmitted to the test circuit through the MOS transistors MT1-MT4. Normally, MOS transistors do not have large load driving abilities. Hence, it takes a long time to charge parasitic capacitors coupled to the data buses DB1-DB4. Normally, the data buses DB1-DB4 extending to the sense amplifiers SA1-SA4 from the memory cells are long. As a result, it is very difficult to test the memory cells at a high speed. Second, there is a delay in transferring the pass/fail signal output by the test circuit TC to the buffer BUF4 through the MOS transistors MT6. Thus, data transmitted by the buffer BUF4 lags behind other data transmitted by the buffers BUF1-BUF3 since the MOS transistors MT5 are interposed only between the sense amplifier SA4 and the buffer BUF4. Third, it is impossible to supervise the sense amplifier SA4 since the signals transmitted by the test circuit TC do not pass the sense amplifier SA4.
The conventional circuit shown in FIG. 2 has the following disadvantages. First, the gates G1 and G2, each having 16 inputs, must be used. Such multiple-input gates have complex structures and large delay times. Thus, it takes a much longer time to obtain the signal PTO than it does to obtain it with the normal data read operation. Thus, no correlation between the test mode and the normal mode can be obtained. Further, the pass/fail signal is transmitted by a special terminal different from a read data output terminal (not shown). Hence, a large number of terminals must be used.